`include "i2c_mst_seq.sv"
`include "i2c_mst_drv.sv"
`include "i2c_mst_mon.sv"

typedef uvm_sequencer #(i2c_trans) i2c_mst_seqr;

class i2c_mst_agt extends uvm_agent;
    i2c_mst_seq seqr;
    i2c_mst_drv drv;
    i2c_mst_mon mon;

    uvm_analysis_port #(i2c_trans) analysis_port;

    `uvm_component_utils(i2c_mst_agt)

    function new(string name, uvm_component parent);
        super.new(name, parent);
        `uvm_info("TRACE", $sformatf("%m"), UVM_HIGH)
    endfunction

    virtual function void build_phase(uvm_phase phase);
        super.build_phase(phase);
        `uvm_info("TRACE", $sformatf("%m"), UVM_HIGH)
        
        //create the apb_mst_seqr/apb_mst_drv/apb_mst_mon
        if (is_active == UVM_ACTIVE) begin
            seqr = i2c_mst_seq::type_id::create("seqr", this);
            drv  = i2c_mst_drv::type_id::create("drv", this);
        end
        mon  = i2c_mst_mon::type_id::create("mon", this);
    endfunction

    virtual function void connect_phase(uvm_phase phase);
        super.connect_phase(phase);
        `uvm_info("TRACE", $sformatf("%m"), UVM_HIGH)

        if (is_active == UVM_ACTIVE) begin
            drv.seq_item_port.connect(seqr.seq_item_export);
        end

        this.analysis_port = mon.analysis_port;
    endfunction

    virtual function void start_of_simulation_phase(uvm_phase phase);
        super.start_of_simulation_phase(phase);
        `uvm_info("TRACE", $sformatf("%m"), UVM_HIGH)
    endfunction: start_of_simulation_phase


endclass